VHDL LAB MANUAL Sri Siddhartha Institute of Technology

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VHDL Lab Manual,Sl No Experiment Name Page No,1 ISE Quick Start Tutorial 3. 2 Full Adder Data Flow Behavioral 13,3 Full Adder Structural 14. 4 Multiplexer 8 1 15,5 Demultiplexer 1 8 16,6 Encoder without Priority 17. 7 Encoder with Priority 18,8 Decoder 3 8 19,9 2 Bit Comparator 20. 10 Binary to Gray 21,11 Gray to Binary 22,12 JK Flip Flop 23.
13 T Flip Flop 24,14 D Flip Flop 25,15 Asynchronous Binary Up Counter 26. 16 Synchronous Binary Up Counter 27,17 BCD Up Counter 28. 18 BCD Down Counter 29,19 DC Motor Interface 30,20 Stepper Motor Interface 31. 21 Relay Interface 32,22 Seven Segment Display Interface 33. 23 Multiplexer 8 1 Structural 34,24 Binary to Gray Structural 35.
25 Gray to Binary Structural 36,26 Decoder 3 8 Structural 37. 27 JK Flip Flop Structural 38,28 T Flip Flop Structural 39. 29 D Flip Flop Structural 40,30 1 Bit Comparator Structural 41. 31 Pin Details 43,Department of E C SSIT Tumkur Page 1. VHDL Lab Manual,Department of E C SSIT Tumkur Page 2.
VHDL Lab Manual,ISE Quick Start Tutorial,Getting Started. Starting the ISE Software, For Windows users start ISE from the Start menu by selecting. Start Programs Xilinx ISE 7 Project Navigator, The ISE Project Navigator opens The Project Navigator lets you manage the sources and. processes in your ISE project All of the tasks in the Quick Start Tutorial are managed from within. Project Navigator,Stopping and Restarting a Session. At any point during this tutorial you can stop your session and continue at a later time. To stop the session, Save all source files you have opened in other applications.
Exit the software ISE and other applications, The current status of the ISE project is maintained when exiting the software. To restart your session start the ISE software again ISE displays the contents and state of your. project with the last saved changes,Accessing Help. At any time during the tutorial you can access online help for additional information about a. variety of topics and procedures in the ISE software as well as related tools. To open Help you may do either of the following, Press F1 to view Help for the specific tool or function that you have selected or highlighted. Launch the ISE Help Contents from the Help menu It contains information about creating. and maintaining your complete design flow in ISE,Creating a New Project in ISE. In this section you will create a new ISE project A project is a collection of all files necessary to. create and to download a design to a selected FPGA or CPLD device. To create a new project for this tutorial, 1 Select File New Project The New Project Wizard appears.
2 First enter a location directory path for the new project. 3 Type tutorial in the Project Name field When you type tutorial in the Project Name field a. tutorial subdirectory is created automatically in the directory path you selected. 4 Select HDL from the Top Level Module Type list indicating that the top level file in your. project will be HDL rather than Schematic or EDIF, 5 Click Next to move to the project properties page. 6 Fill in the properties in the table as shown below. Device Family CoolRunner XPLA3 CPLDs,Device xcr3128xl. Package TQ144,Speed Grade 7,Top Level Module Type HDL. Synthesis Tool XST VHDL Verilog,Simulator ModelSim. Generated Simulation Language VHDL or Verilog depending on the language you want. to use when running behavioral simulation,Department of E C SSIT Tumkur Page 3.
VHDL Lab Manual, When the table is complete your project properties should look like the following. 7 Click Next to proceed to the Create New Source window in the New Project Wizard At the end of the next section your new project will be. Creating an HDL Source, In this section you will create a top level HDL file for your design Determine the language that you wish to use for the tutorial Then continue either to the. Creating a VHDL Source section below, This simple AND Gate design has two inputs A and B This design has one output called C. 1 Click New Source in the New Project Wizard to add one new source to your project. 2 Select VHDL Module as the source type in the New Source dialog box. 3 Type in the file name andgate, 4 Verify that the Add to project checkbox is selected. 5 Click Next,6 Define the ports for your VHDL source.
In the Port Name column type the port names on three separate rows A B and C. In the Direction column indicate whether each port is an input output or inout For A and B select in from the list For C select out from the. Department of E C SSIT Tumkur Page 4,VHDL Lab Manual. 7 Click Next in the Define VHDL Source dialog box, 8 Click Finish in the New Source Information dialog box to complete the new source file template. 9 Click Next in the New Project Wizard,10 Click Next again. 11 Click Finish in the New Project Information dialog box. ISE creates and displays the new project in the Sources in Project window and adds the andgate vhd file to the project. 12 Double click on the andgate vhd file in the Sources in Project window to open the VHDL file in the ISE Text Editor. The andgate vhd file contains,o Header information. o Library declaration and use statements, o Entity declaration for the counter and an empty architecture statement.
13 In the header section fill in the following fields. Design Name andgate vhd,Project Name andgate,Target Device xcr3128xl TQ144. Description This is the top level HDL file for an up down counter. Dependencies None, Note It is good design practice to fill in the header section in all source files. 14 Below the end process statement enter the following line. 15 Save the file by selecting File Save,Checking the Syntax of the New Counter Module. When the source files are complete the next step is to check the syntax of the design Syntax errors and typos can be found using this step. 1 Select the counter design source in the ISE Sources window to display the related processes in the Processes for Source window. 2 Click the next to the Synthesize XST process to expand the hierarchy. 3 Double click the Check Syntax process, When an ISE process completes you will see a status indicator next to the process name. If the process completed successfully a green check mark appears. If there were errors and the process failed a red X appears. A yellow exclamation point means that the process completed successfully but some warnings occurred. An orange question mark means the process is out of date and should be run again. Department of E C SSIT Tumkur Page 5,VHDL Lab Manual.
4 Look in the Console tab of the Transcript window and read the output and status messages produced by any process that you run. Caution You must correct any errors found in your source files If you continue without valid. syntax you will not be able to simulate or synthesize your design. Simulation, 1 Double click Launch ModelSim Simulator in the Process View window. 2 Right Click a to open a context menu,3 Select Force or Clock to add the signal. Department of E C SSIT Tumkur Page 6,VHDL Lab Manual. 4 Define the Clock or Force signal to load appropriate signal. 5 Run the simulation by clicking the Run icon in the Main or Wave window toolbar. 6 Waveform can be observed in the wave window,Department of E C SSIT Tumkur Page 7. VHDL Lab Manual, 7 Click the Run All icon on the Main or Wave window toolbar The simulation continues running until you execute a break command.
8 Click the Break icon The simulation stops running. 9 To restart the simulation click the Restart icon to reload the design elements and reset the simulation time to zero The Restart dialog that appears. gives you options on what to retain during the restart Click the Restart button in the Restart dialog. Assigning Pin Location, 1 Double click the Assign Package Pins process found in the User Constraints process group ISE runs the Synthesis and Translate steps. and automatically creates a User Constraints File UCF You will be prompted with the following message. Department of E C SSIT Tumkur Page 8,VHDL Lab Manual. 2 Click Yes to add the UCF file to your project The counter ucf file is added to your project and is visible in the Sources in Project. window The Xilinx Constraints Editor opens automatically. 3 Now the Xilinx Pinout and Area Constraints Editor PACE opens. 4 You can see your I O Pins listed in the Design Object List window Enter a pin location for each pin in the Loc column as specified below. 5 Click on the Package View tab at the bottom of the window to see the pins you just added Put your mouse over grid number to verify the. pin assignment, 5 Select File Save You are prompted to select the bus delimiter type based on the synthesis tool you are using Select XST Default. and click OK,6 Close PACE,Department of E C SSIT Tumkur Page 9. VHDL Lab Manual,Creating Configuration Data, The final phase in the software flow is to generate a program file and configure the device.
Generating a Program File, The Program File is a encoded file that is the equivalent of the design in a form that can be downloaded into the CPLD device. 1 Double Click the Generate Programming File process located near the bottom of the Processes for Source window. The Program File is created It is written into a file called andgate jed This is the actual configuration data. Configuring the Device, iMPACT is used to configure your FPGA or CPLD device This is the last step in the design process This section provides simple instructions for. configuring a Spartan 3 xc3s200 device connected to your PC. Note Your board must be connected to your PC before proceeding If the device on your board does not match. the device assigned to the project you will get errors Please refer to the iMPACT Help for more information To. access the help select Help Help Topics,To configure the device. 1 Click the sign to expand the Generate Programming File processes. 2 Double click the Configure Device iMPACT process iMPACT opens and the Configure Devices dialog box is displayed. Department of E C SSIT Tumkur Page 10,VHDL Lab Manual. 3 In the Configure Devices dialog box verify that Boundary Scan Mode is selected and click Next. 4 Verify that Automatically connect to cable and identify Boundary Scan chain is selected and click. 5 If you get a message saying that there was one device found click OK to continue. 6 The iMPACT will now show the detected device right click the device and select New Configuration File. 7 The Assign New Configuration File dialog box appears Assign a configuration file to each device in the JTAG chain Select the. andgate jed file and click Open, 8 Right click on the counter device image and select Program to open the Program Options dialog box.
9 Click OK to program the device ISE programs the device and displays Programming Succeeded if the operation was successful. 10 Close iMPACT without saving,Department of E C SSIT Tumkur Page 11. VHDL Lab Manual,Department of E C SSIT Tumkur Page 12. VHDL Lab Manual,1 VHDL CODE FOR FULL ADDER,Full Adder. A B CiC S Co,0 0 1 1 0 XPRESSIONS,0 1 1 0 1 S A B Ci. 1 0 0 1 0 O A B Ci AB,libraary IEEE,use IEEE STD LO OGIC 1164 A ALL.
use IEEE STD LO OGIC ARITH ALL,use IEEE STD LO OGIC UNSIGNED ALL. entity faa1 is,Port a b ci in STTD LOGIC s co out STD. archhitecture Beh havioral of faa1 is,s a xorr b xor ci. a b or b anda ci or ci and,end Behavioral,ODE FOR FULL ADDER BEEHAVIORAL. libraary IEEE,use IEEE STD LO OGIC 1164 A ALL,use IEEE STD LO OGIC ARITH ALL.
use IEEE STD LO OGIC UNSIGNED ALL,entity faa1 is,Port a b ci in STTD LOGIC s co out STD. archhitecture Beh havioral of faa1 is,process a b ci. s a xorr b xor ci,a b or b anda ci or ci and,end process. end Behavioral,ment of E C SSIT Tumku,ur Page 13,VHDL Lab Manual. 2 VHDL CODE FOR FULL ADDER STRUCTURAL,library IEEE.
use IEEE STD LOGIC 1164 ALL,use IEEE STD LOGIC ARITH ALL. use IEEE STD LOGIC UNSIGNED ALL,entity fa1 is,Port a b cin in STD LOGIC. s cout out STD LOGIC,architecture struct of fa1 is. component and21, port a b in std logic components entity and architecture. c out std logic must be declared separately,end component.
component xor21, port a b in std logic components entity and architecture. c out std logic must be declared separately,end component. component or31, port a b in std logic components entity and architecture. d out std logic must be declared separately,end component. signal s1 s2 s3 std logic,u1 xor21 port map a b s1.
u2 xor21 port map s1 cin s,u3 and21 port map a b s2. u4 and21 port map s1 cin s3,u6 or31 port map s2 s3 cout. VHDL Lab Manual Department of E amp C SSIT Tumkur Page 10 Creating Configuration Data The final phase in the software flow is to generate a program file and configure the device Generating a Program File The Program File is a encoded file that is the equivalent of the design in a form that can be downloaded into the CPLD device 1 Double

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