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Channabasaveshwara Institute of Technology,An ISO 9001 2008 Certified Institution. NH 206 B H Road Gubbi Tumkur 572 216 Karnataka, Department of Electronics and Communication Engineering. Version 1 0,Prepared by Reviewed by,Mr Sanjay C P Mr Nagaraja P. Mrs Smitha U V Associate Professor,Mrs Sangeetha G. Mrs Kouser Taj,Assistant Professor,Approved by,Prof Rajendra.
Professor Head,Dept of ECE,QMP 7 1 D D,Channabasaveshwara Institute of Technology. An ISO 9001 2008 Certified Institution,NH 206 B H Road Gubbi Tumkur 572 216 Karnataka. DEPARTMENT OF ELECTRONICS COMMUNICATION ENGINEERING. HDL LAB SYLLABUS,Subject Code 10ECL48 IA Marks 25,No of Practical Hrs Week 03 Exam Hours 03. Total no of Practical Hrs 42 Exam Marks 50, Note Programming can be done using any compiler Download the programs on a. FPGA CPLD boards such as Apex Acex Max Spartan Sinfi TK Base or equivalent. and performance testing may be done using 32 channel pattern generator and logic. analyzer apart from verification by simulation with tools such as Altera Modelsim. or equivalent,PROGRAMMING using VHDL Verilog,1 Write HDL code to realize all the logic gates.
2 Write a HDL program for the following combinational designs. a 2 to 4 decoder,b 8 to 3 encoder without priority with priority. c 8 to 1 multiplexer,d 4 bit binary to gray converter. e Multiplexer de multiplexer comparator, 3 Write a HDL code to describe the functions of a Full Adder Using three. modeling styles, 4 Write a model for 32 bit ALU using the schematic diagram shown below. ALU should use combinational logic to calculate an output based on the. four bit op code input, ALU should pass the result to the out bus when enable line in high and.
tri state the out bus when the enable line is low, ALU should decode the 4 bit op code according to the given in example. OPCODE ALU OPERATION,3 A Complement,7 A NAND B, 5 Develop the HDL Code for the following flip flops SR D JK and T. 6 Design 4 bit binary BCD counters Synchronous reset and asynchronous. reset and any sequence counters, INTERFACING at least four of the following must be covered using VHDL. 1 Write HDL code to display messages on the given seven segment display and. LCD and accepting Hex key pad input data, 2 Write HDL code to control speed direction of DC and Stepper motor. 3 Write HDL code to accept 8 channel Analog signal Temperature sensors and. display the data on LCD panel or Seven segment display. 4 Write HDL code to generate different waveforms Sine Square Triangle. Ramp etc using DAC change the frequency and amplitude. 5 Write HDL code to simulate Elevator operations, 6 Write HDL code to control external lights using relays.
OBJECTIVES, To introduce Xilinx compiler and in built simulator. To describe the simulation and synthesis of the systems using Hardware. Description Languages and explain its various abstraction levels. To code generate and implement on FPGA Kit, To interface the FPGA kit with different external devices. The student will be able to, Write efficient hardware designs both in VHDL and Verilog and perform. high level HDL simulation synthesis and verify the expected output. Explain different levels of abstraction with the programming examples. To generate and implement the program s on FPGA Kit. Interface the FPGA with different external devices such as motors relays. DAC seven segment and LCD displays,GENERAL INSTRUCTIONS TO STUDENTS. 1 Students should come with thorough preparation for the experiment to be conducted. 2 Students should take prior permission from the concerned faculty before availing the leave. 3 Students should come with formals and to be present on time in the laboratory. 4 Students will not be permitted to attend the laboratory unless they bring the practical record. fully completed in all respects pertaining to the experiment conducted in the previous class. 5 Students will be permitted to attend laboratory unless they bring the observation book fully. completed in all respects pertaining to the experiment conducted in the present class. 6 They should obtain the signature of the staff in charge in the observation book after. completing each experiment, 7 Practical record and observation book should be maintained neatly.
Record Marks,Manual Marks,Name of the Experiment,Submission. Conduction Repetition,PROGRAMMING using VHDL Verilog. 01 HDL code to realize all the,logic gates,02 HDL program for the following. combinational designs,a 2 to 4 decoder,b 8 to 3 encoder without priority. with priority,c 8 to 1 multiplexer,d 4 bit binary to gray converter.
e De multiplexer comparator,03 HDL code to describe the. functions of a Full Adder Using,three modeling styles. 04 HDL code to realize 32 bit ALU,05 HDL Code for the following flip. flops SR D JK and T,06 4 bit binary BCD counters,Synchronous reset and. asynchronous reset and any,sequence counters,INTERFACING.
07 HDL code to display numbers on,the given seven segment display. using Hex keypad input data,08 HDL code to control speed. direction of DC and Stepper,09 HDL code to generate different. waveforms Sine Square,Triangle Ramp etc using DAC,change the frequency. 10 HDL code to control external,lights using relays.
Sl Page No,No EXPERIMENT NAMES,1 HDL code to realize all the gates 1 4. HDL program for the following combinational designs. 2 a 2 to 4 decoder, b 8 to 3 encoder without priority with priority 5 32. c 8 to 1 multiplexer,d 4 bit binary to gray converter. e Demux and Comparator, 3 HDL code to describe the functions of a Full adder using all modeling 33 40. 4 HDL model for 8 bit ALU 41 44, 5 HDL codes for the following flip flops SR D JK T 45 60.
6 HDL code for 4 bit binary BCD counters synchronous reset and. asynchronous reset and any sequence counters 61 80. INTERFACING PROGRAMS, 7 HDL code to display messages on the Seven Segment Display 81 84. 8 HDL code to control speed direction of dc and stepper motor 85 90. 9 VHDL code to generate different waveforms Square Triangle Ramp. etc using DAC change the frequency and amplitude 91 98. 10 VHDL code to control lights using relays 99 100. 11 HDL code to accept 8 channel analog signals temperature sensors and 101 112. display the data on LCD panel or Seven Segment Display. 12 VHDL code to simulate elevator operations 113 122. EXTRA PROGRAMS,13 HDL code to 4 Bit Braun multiplier 123 124. Sample Viva Questions,Question Bank,HDL Lab 10ECL48 2015 16. Introduction to Xilinx ISE, Xilinx ISE means Xilinx Integrated Software Environment ISE i e. programmable logic design tool in electronics industry This Xilinx design. software suite allows taking design from design entry through Xilinx device. programming The ISE Project Navigator manages and processes design. through several steps in the ISE design flow These steps are Design Entry. Synthesis Implementation Simulation Verification and Device. Configuration Xilinx is one of most popular software tool used to synthesize. Tool Procedure,1 Double click on Project Navigator Icon.
2 Select new project in file menu, 3 Enter the project name and location as shown below and hit Next. Dept of ECE CIT Gubbi,HDL Lab 10ECL48 2015 16, 4 Select the Family Device Package and speed as per the requirements. and hit Next, 5 Create a new source by using new source icon or right click on the. device project folder to create new source, 6 Select the appropriate source type and enter the file name in New. Source Wizard window and hit Next,Dept of ECE CIT Gubbi.
HDL Lab 10ECL48 2015 16, 7 Enter the architecture name dataflow behavioral structural port. name and select the direction This will create vhd source file Hit. Next and finish the initial project creation, 8 Write complete VHDL Verilog codeimplementation and save. 9 Click on implementation and check for syntax using Check syntax. option under synthesize tab If any error edit and correct VHDL Verilog. code and repeat check syntax until zero errors, 10 Double click on ISIM simulator by selecting simulation mode to. complete the functional simulation of your design,Dept of ECE CIT Gubbi. HDL Lab 10ECL48 2015 16,Procedure for Interfacing, 1 Repeat the steps 1 to 10 from the tool procedure.
2 Make the connection between appropriate FRC s of the FPGA board and. the DIP switch connector of the GPIOcard 2, 3 Make the connection between appropriate FRC s of the FPGA board and. the LED connector of the GPIOcard 2, 4 Right click on the device and select New Source Select the option. Implementation constraint File and provide the file name and click on. next and then hit Finish This creates an ucf file, 6 Double click on the added ucf file and assign the pin numbers to inputs. and outputs referring to FRC sheet using the syntax as shown Save the. constraint file,Dept of ECE CIT Gubbi,HDL Lab 10ECL48 2015 16. 7 Connect USB programmer for FPGA between FPGA kit and USB port of. your computer, 8 Go to process window select the Vhdl or Verilog file and click on.
configure target device,9 Click OK for the warning below. 10 Select boundary scan to impact the target device. Dept of ECE CIT Gubbi,HDL Lab 10ECL48 2015 16, 11 Right click on the impact window to establish a connection between. system and FPGA by selecting INTIALIZE CHAIN option. 12 Both prom device and FPGA device gets identified after step 10 and. bypass the procedure to select only FPGA which of main interest. 13 Now choose device 2 FPGA Xc6Slx9 and hit ok to complete the impact. HDL Lab 10ECL48 B E IV Semester Lab Manual 2015 16 Name USN Batch Section Design 4 bit binary BCD counters Synchronous reset and asynchronous UHVHW D QG DQV HTXHQFH FRXQWHUV INTERFACING at least fou r of the following must be covered using VHDL Verilog 1 Write HDL code to display messages on the given seven segment display and LCD and accepting

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