An Introduction To Very Long Instruction Word VLIW

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Philips Semiconductors,Introduction to VLIW Computer Architecture. INTRODUCTION AND MOTIVATION, Currently in the mid 1990s IC fabrication technology is advanced enough to allow unprecedented. implementations of computer architectures on a single chip Also the current rate of process advancement. allows implementations to be improved at a rate that is satisfying for most of the markets these. implementations serve In particular the vendors of general purpose microprocessors are competing for. sockets in desktop personal computers including workstations by pushing the envelopes of clock rate raw. operating speed and parallel execution, The market for desktop microprocessors is proving to be extremely dynamic In particular the x86 market. has surprised many observers by attaining performance levels and price performance levels that many. thought were out of reach The reason for the pessimism about the x86 was its architecture instruction. set Indeed with the advent of RISC architectures the x86 is now recognized as a deficient instruction set. Instruction set compatibility is at the heart of the desktop microprocessor market Because the application. programs that end users purchase are delivered in binary directly executable by the microprocessor form. the end users desire to protect their software investments creates tremendous instruction set inertia. There is a different market though that is much less affected by instruction set inertia This market is. typically called the embedded market and it is characterized by products containing factory installed. software that runs on a microprocessor whose instruction set is not readily evident to the end user. Although the vendor of the product containing the embedded microprocessor has an investment in the. embedded software just like end users with their applications there is considerably more freedom to. migrate embedded software to a new microprocessor with a different instruction set To overcome this. lower level of instruction set inertia all it takes is a sufficiently better set of implementation characteristics. particularly absolute performance and or price performance. This lower level of instruction set inertia gives the vendors of embedded microprocessors the freedom and. initiative to seek out new instruction sets The relative success of RISC microprocessors in the high end of. the embedded market is an example of innovation by microprocessor vendors that produced a benefit large. enough to overcome the market s inertia To the vendors disappointment the benefits of RISCs have not. been sufficient to overcome the instruction set inertia of the mainstream desktop computer market. Because of advances in IC fabrication technology and advances in high level language compiler technology it. now appears that microprocessor vendors are compelled by the potential benefits of another change in. microprocessor instruction sets As before the embedded market is likely to be first to accept this change. The new direction in microprocessor architecture is toward VLIW very long instruction word instruction. sets VLIW architectures are characterized by instructions that each specify several independent operations. This is compared to RISC instructions that typically specify one operation and CISC instructions that typically. specify several dependent operations VLIW instructions are necessarily longer than RISC or CISC. instructions thus the name,Philips Semiconductors,Introduction to VLIW Computer Architecture. The key to higher performance in microprocessors for a broad range of applications is the ability to exploit. fine grain instruction level parallelism Some methods for exploiting fine grain parallelism include. pipelining,multiple processors,superscalar implementation.
specifying multiple independent operations per instruction. Pipelining is now universally implemented in high performance processors Little more can be gained by. improving the implementation of a single pipeline, Using multiple processors improves performance for only a restricted set of applications. Superscalar implementations can improve performance for all types of applications Superscalar super. beyond scalar one dimensional means the ability to fetch issue to execution units and complete more. than one instruction at a time Superscalar implementations are required when architectural compatibility. must be preserved and they will be used for entrenched architectures with legacy software such as the x86. architecture that dominates the desktop computer market. Specifying multiple operations per instruction creates a very long instruction word architecture or VLIW A. VLIW implementation has capabilities very similar to those of a superscalar processor issuing and. completing more than one operation at a time with one important exception the VLIW hardware is not. responsible for discovering opportunities to execute multiple operations concurrently For the VLIW. implementation the long instruction word already encodes the concurrent operations This explicit. encoding leads to dramatically reduced hardware complexity compared to a high degree superscalar. implementation of a RISC or CISC, The big advantage of VLIW then is that a highly concurrent parallel implementation is much simpler and. cheaper to build than equivalently concurrent RISC or CISC chips VLIW is a simpler way to build a. superscalar microprocessor,ARCHITECTURE VS IMPLEMENTATION. The word architecture in the context of computer science is often misused Used accurately architecture. refers to the instruction set and resources available to someone who writes programs The architecture is. what is described in a definition document often called a user s manual Thus architecture contains. instruction formats instruction semantics operation definitions registers memory addressing modes. characteristics of the address space linear segmented special address regions and anything else a. programmer would need to know, An implementation is the hardware design that realizes the operations specified by the architecture The. implementation determines the characteristics of a microprocessor that are most often measured price. performance power consumption heat dissipation numbers of pins operating frequency and so on. Architecture and implementation are separate but they do interact As many researchers into computer. architecture discovered between the mid 1970s and 1980s architecture can have a dramatic effect on the. quality of an implementation In the mid 1980s IC process technology could fabricate a microcoded. implementation of a CISC instruction set and a tiny cache or MMU For about the same cost this same. process technology could fabricate a pipelined implementation of a simple RISC instruction set including. Philips Semiconductors,Introduction to VLIW Computer Architecture.
large register file with an MMU At the time however chip technology was not dense enough to build a. cost effective pipelined implementation of a CISC instruction set As a result pipelined RISC chips enjoyed. a dramatic performance advantage and made a compelling case for RISC architectures. The important point is that a range of implementations of any architecture can be built but architecture. influences the quality and cost effectiveness of those implementations The influence is exerted largely in the. trade offs that must be made to accommodate complexity associated with the instruction set The more. chip area spent on logic to decode instructions and implement irregularities the less that can be devoted to. performance enhancing features,ARCHITECTURE COMPARISON CISC RISC AND VLIW. From the larger perspective RISC CISC and VLIW architectures have more similarities than differences. The differences that exist however have profound effects on the implementations of these architectures. Obviously these architectures all use the traditional state machine model of computation Each instruction. effects an incremental change in the state memory registers of the computer and the hardware fetches. and executes instructions sequentially until a branch instruction causes the flow of control to change. ARCHITECTURE CISC RISC VLIW,CHARACTERISTIC, INSTRUCTION SIZE Varies One size usually 32 bits One size. INSTRUCTION FO RMAT Field placement varies Regular consistent Regular consistent placement of. placement of fields fields, INSTRUCTION Varies from simple to Almost always one simple Many simple independent. SEMANTICS complex possibly many operation operations. dependent operations,per instruction, REGISTERS Few sometimes special Many general purpose Many general purpose. MEMORY REFE RENCES Bundled with operations Not bundled with Not bundled with operations. in many different types of operations i e load store i e load store architecture. instructions architecture, HARDWARE DESIGN Exploit microcoded Exploit implementations Exploit implementations with.
FOCUS implementations with one pipeline and multiple pipelines no microcode. no microcode no complex dispatch logic,PICTURE OF FIVE. TYPICAL INSTRU CTIONS, The differences between RISC CISC and VLIW are in the formats and semantics of the instructions Table 1. compares architecture characteristics, CISC instructions vary in size often specify a sequence of operations and can require serial slow decoding. algorithms CISCs tend to have few registers and the registers may be special purpose which restricts the. ways in which they can be used Memory references are typically combined with other operations such as. add memory to register CISC instruction sets are designed to take advantage of microcode. RISC instructions specify simple operations are fixed in size and are easy quick to decode RISC. architectures have a relatively large number of general purpose registers Instructions can reference main. Philips Semiconductors,Introduction to VLIW Computer Architecture. memory only through simple load register from memory and store register to memory operations RISC. instruction sets do not need microcode and are designed to simplify pipelining. VLIW instructions are like RISC instructions except that they are longer to allow them to specify multiple. independent simple operations A VLIW instruction can be thought of as several RISC instructions joined. together VLIW architectures tend to be RISC like in most attributes. Figure 1 shows a C language code fragment containing small function definition This function adds a local. variable to a parameter passed from the caller of the function. The implementation of this function in CISC RISC and VLIW code is also shown This example is. extremely unfair to the RISC and VLIW machines but it illustrates the differences between the. architectures, The CISC code consists of one instruction because the CISC architecture has an add instruction that can.
encode a memory address for the destination So the CISC instruction adds the local variable in register r2. to the memory based parameter The encoding of this CISC instruction might take four bytes on some. hypothetical machine, The RISC code is artificially inefficient Normally a good compiler would pass. the parameter in a register which would make the RISC code consist of only a. single register to register add instruction For the sake of illustration however. the code will consist of three instructions as shown These three instructions. load the parameter to a register add it to the local variable already in a register. and then store the result back to memory Each RISC instruction requires four. The VLIW code is similarly hampered by poor register allocation The example. VLIW architecture shown has the ability to simultaneously issue three. operations The first slot group of four bytes is for branch instructions the. middle slot is for ALU instructions and the last slot is for the load store unit. Since the three RISC operations needed to implement the code fragment are. dependent it is not possible to pack the load and add in the same VLIW. instruction Thus three separate VLIW instructions are necessary. With the code fragment as shown the VLIW instruction is depressingly. inefficient from the point of view of code destiny In a real program situation. the compiler for the VLIW would use several program optimization techniques. to fill all three slots in all three instructions It is instructive to contemplate the. performance each machine might achieve for this code We need to assume. that each machine has an efficient pipelined implementation. Philips Semiconductors,Introduction to VLIW Computer Architecture. A CISC machine such as the 486 or Pentium would be able to execute the code fragment in three cycles. A RISC machine would be able to execute the fragment in three cycles as well but the cycles would likely. be faster than on the CISC, The VLIW machine assuming three fully packed instructions would effectively execute the code for this. fragment in one cycle To see this observe that the fragment requires three out of nine slots for one third. use of resources One third of three cycles is one cycle. To be even more accurate we can assume good register allocation as shown. in Figure 2 This example may actually be giving the CISC machine a slight. unfair advantage since it will not be possible to allocate parameters to registers. on the CISC as often as is possible for the RISC and VLIW. The CISC and RISC machines with good register allocation would take on. The new direction in microprocessor architecture is toward VLIW very long instruction word instruction sets VLIW architectures are characterized by instructions that each specify several independent operations This is compared to RISC instructions that typically specify one operation and CISC instructions that typically

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